move similar components into new hal module

This commit is contained in:
Garen Tyler 2024-02-23 02:39:17 -07:00
parent 4ea64e0b6b
commit 6ef3df9177
Signed by: garentyler
GPG Key ID: D7A048C454CB7054
36 changed files with 208 additions and 108 deletions

52
\ Normal file
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@ -0,0 +1,52 @@
use crate::hal::arch::riscv::{asm, MIE_MTIE, MSTATUS_MIE};
use crate::NCPU;
use core::ptr::addr_of;
// Core Local Interrupter (CLINT), which contains the timer.
pub const CLINT: usize = 0x2000000;
const CLINT_MTIME: usize = CLINT + 0xbff8;
extern "C" {
pub fn timervec();
}
#[no_mangle]
pub static mut timer_scratch: [[u64; 5]; NCPU] = [[0u64; 5]; NCPU];
fn clint_mtimecmp(hartid: usize) -> *mut u64 {
(CLINT + 0x4000 + (8 * hartid)) as *mut u64
}
/// Arrange to receive timer interrupts.
///
/// They will arrive in machine mode at
/// at timervec in kernelvec.S,
/// which turns them into software interrupts for
/// devintr() in trap.c.
pub unsafe fn timerinit() {
// Each CPU has a separate source of timer interrupts.
let id = asm::r_mhartid() as usize;
// Ask the CLINT for a timer interrupt.
// cycles, about 1/10th second in qemu
let interval = 1_000_000u64;
*clint_mtimecmp(id) = *(CLINT_MTIME as *const u64) + interval;
// Prepare information in scratch[] for timervec.
// scratch[0..=2]: Space for timervec to save registers.
// scratch[3]: Address of CLINT MTIMECMP register.
// scratch[4]: Desired interval (in cycles) between timer interrupts.
let scratch: &mut [u64; 5] = &mut timer_scratch[id];
scratch[3] = clint_mtimecmp(id) as usize as u64;
scratch[4] = interval;
asm::w_mscratch(addr_of!(scratch[0]) as usize as u64);
// Set the machine-mode trap handler.
asm::w_mtvec(timervec as usize as u64);
// Enable machine-mode interrupts.
asm::w_mstatus(asm::r_mstatus() | MSTATUS_MIE);
// Enable machine-mode timer interrupts.
asm::w_mie(asm::r_mie() | MIE_MTIE);
}

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@ -10,5 +10,10 @@ license = "LGPL-3.0-only"
[dependencies] [dependencies]
arrayvec = { version = "0.7.4", default-features = false } arrayvec = { version = "0.7.4", default-features = false }
[features]
default = ["qemu-riscv64"]
qemu-riscv64 = []
milk-v = []
[lib] [lib]
crate-type = ["staticlib"] crate-type = ["staticlib"]

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@ -1,3 +0,0 @@
// Virtio MMIO interface
pub const VIRTIO0: usize = 0x10001000;
pub const VIRTIO0_IRQ: usize = 1;

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@ -1,8 +0,0 @@
/// QEMU test interface. Used for power off and on.
pub const QEMU_POWER: usize = 0x100000;
pub unsafe fn shutdown() -> ! {
let qemu_power = QEMU_POWER as *mut u32;
qemu_power.write_volatile(0x5555u32);
unreachable!();
}

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@ -11,9 +11,9 @@
pub mod printf; pub mod printf;
use crate::{ use crate::{
arch::virtual_memory::{either_copyin, either_copyout},
fs::file::{devsw, CONSOLE}, fs::file::{devsw, CONSOLE},
hardware::uart::BufferedUart, hal::arch::virtual_memory::{either_copyin, either_copyout},
hal::hardware::uart::BufferedUart,
proc::{ proc::{
process::{procdump, Process}, process::{procdump, Process},
scheduler::wakeup, scheduler::wakeup,
@ -22,7 +22,7 @@ use crate::{
}; };
use core::ptr::addr_of_mut; use core::ptr::addr_of_mut;
pub static UART0: &BufferedUart = &crate::hardware::UARTS[0].1; pub static UART0: &BufferedUart = &crate::hal::platform::UARTS[0].1;
pub const BACKSPACE: u8 = 0x00; pub const BACKSPACE: u8 = 0x00;
pub const INPUT_BUF_SIZE: usize = 128; pub const INPUT_BUF_SIZE: usize = 128;

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@ -2,8 +2,8 @@
use super::inode::{iput, readi, stati, writei, Inode, InodeLockGuard}; use super::inode::{iput, readi, stati, writei, Inode, InodeLockGuard};
use crate::{ use crate::{
arch::virtual_memory::copyout,
fs::{log, stat::Stat}, fs::{log, stat::Stat},
hal::arch::virtual_memory::copyout,
io::pipe::Pipe, io::pipe::Pipe,
proc::process::Process, proc::process::Process,
sync::mutex::Mutex, sync::mutex::Mutex,

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@ -1,7 +1,5 @@
#[cfg(target_arch = "riscv64")] #[cfg(target_arch = "riscv64")]
mod riscv; pub mod riscv;
#[cfg(target_arch = "riscv64")]
pub use riscv::hardware;
pub mod trap; pub mod trap;
@ -12,12 +10,12 @@ pub mod cpu {
pub mod interrupt { pub mod interrupt {
#[cfg(target_arch = "riscv64")] #[cfg(target_arch = "riscv64")]
pub use super::riscv::{ pub use crate::hal::{
asm::{ arch::riscv::asm::{
intr_get as interrupts_enabled, intr_off as disable_interrupts, intr_get as interrupts_enabled, intr_off as disable_interrupts,
intr_on as enable_interrupts, intr_on as enable_interrupts,
}, },
plic::{ hardware::riscv::plic::{
plic_claim as handle_interrupt, plic_complete as complete_interrupt, plicinit as init, plic_claim as handle_interrupt, plic_complete as complete_interrupt, plicinit as init,
plicinithart as inithart, plicinithart as inithart,
}, },
@ -29,8 +27,7 @@ pub mod mem {
pub use super::riscv::{ pub use super::riscv::{
asm::sfence_vma as flush_cached_pages, asm::sfence_vma as flush_cached_pages,
mem::{ mem::{
kstack, Pagetable, PagetableEntry, KERNEL_BASE, PAGE_SIZE, PHYSICAL_END, PTE_R, PTE_U, kstack, Pagetable, PAGE_SIZE, PHYSICAL_END, PTE_R, PTE_W, PTE_X, TRAMPOLINE, TRAPFRAME,
PTE_V, PTE_W, PTE_X, TRAMPOLINE, TRAPFRAME, VIRTUAL_MAX,
}, },
}; };
@ -52,11 +49,6 @@ pub mod virtual_memory {
}; };
} }
pub mod power {
#[cfg(target_arch = "riscv64")]
pub use super::riscv::power::shutdown;
}
pub mod clock { pub mod clock {
#[cfg(target_arch = "riscv64")] #[cfg(target_arch = "riscv64")]
pub use super::riscv::trap::CLOCK_TICKS; pub use super::riscv::trap::CLOCK_TICKS;

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@ -1,10 +1,6 @@
pub mod asm; pub mod asm;
pub mod clint;
pub mod cpu; pub mod cpu;
pub mod hardware;
pub mod mem; pub mod mem;
pub mod plic;
pub mod power;
pub mod start; pub mod start;
pub mod trap; pub mod trap;
pub mod virtual_memory; pub mod virtual_memory;

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@ -1,5 +1,10 @@
use super::{asm, clint, MSTATUS_MPP_MASK, MSTATUS_MPP_S, SIE_SEIE, SIE_SSIE, SIE_STIE}; use crate::{
use crate::{main, NCPU}; hal::{
arch::riscv::{asm, MSTATUS_MPP_MASK, MSTATUS_MPP_S, SIE_SEIE, SIE_SSIE, SIE_STIE},
hardware::riscv::clint,
},
main, NCPU,
};
use core::arch::asm; use core::arch::asm;
#[no_mangle] #[no_mangle]

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@ -1,10 +1,12 @@
use super::{asm, mem::make_satp, SSTATUS_SPIE, SSTATUS_SPP}; use super::{asm, mem::make_satp, SSTATUS_SPIE, SSTATUS_SPP};
use crate::{ use crate::{
hal::{
arch::{ arch::{
hardware::VIRTIO0_IRQ,
interrupt, interrupt,
mem::{PAGE_SIZE, TRAMPOLINE}, mem::{PAGE_SIZE, TRAMPOLINE},
}, },
platform::VIRTIO0_IRQ,
},
println, println,
proc::{ proc::{
cpu::Cpu, cpu::Cpu,
@ -57,7 +59,7 @@ pub unsafe fn devintr() -> i32 {
let irq = interrupt::handle_interrupt(); let irq = interrupt::handle_interrupt();
let mut uart_interrupt = false; let mut uart_interrupt = false;
for (uart_irq, uart) in &crate::hardware::UARTS { for (uart_irq, uart) in &crate::hal::platform::UARTS {
if irq == *uart_irq { if irq == *uart_irq {
uart_interrupt = true; uart_interrupt = true;
uart.interrupt(); uart.interrupt();

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@ -1,18 +1,17 @@
use super::{
asm,
mem::{kstack, make_satp, pte2pa},
plic::PLIC,
power::QEMU_POWER,
};
use crate::{ use crate::{
hal::{
arch::{ arch::{
self, mem::{flush_cached_pages, round_down_page, round_up_page},
hardware::VIRTIO0, riscv::{
asm,
mem::{ mem::{
round_down_page, round_up_page, Pagetable, PagetableEntry, KERNEL_BASE, PAGE_SIZE, kstack, make_satp, pte2pa, Pagetable, PagetableEntry, KERNEL_BASE, PAGE_SIZE,
PHYSICAL_END, PTE_R, PTE_U, PTE_V, PTE_W, PTE_X, TRAMPOLINE, VIRTUAL_MAX, PHYSICAL_END, PTE_R, PTE_U, PTE_V, PTE_W, PTE_X, TRAMPOLINE, VIRTUAL_MAX,
}, },
}, },
},
hardware::riscv::plic::PLIC,
},
mem::{ mem::{
kalloc::{kalloc, kfree}, kalloc::{kalloc, kfree},
memmove, memset, memmove, memset,
@ -42,11 +41,12 @@ pub unsafe fn kvmmake() -> Pagetable {
} }
memset(pagetable.cast(), 0, PAGE_SIZE); memset(pagetable.cast(), 0, PAGE_SIZE);
// QEMU test interface used for power management. for page in &crate::hal::platform::DIRECT_MAPPED_PAGES {
kvmmap(pagetable, QEMU_POWER, QEMU_POWER, PAGE_SIZE, PTE_R | PTE_W); kvmmap(pagetable, *page, *page, PAGE_SIZE, PTE_R | PTE_W);
}
// UART registers // UART registers
for (_, uart) in &crate::hardware::UARTS { for (_, uart) in &crate::hal::platform::UARTS {
kvmmap( kvmmap(
pagetable, pagetable,
uart.base_address, uart.base_address,
@ -56,8 +56,16 @@ pub unsafe fn kvmmake() -> Pagetable {
); );
} }
// VirtIO MMIO disk interface // VirtIO MMIO disk interfaces
kvmmap(pagetable, VIRTIO0, VIRTIO0, PAGE_SIZE, PTE_R | PTE_W); for (_, virtio_disk_addr) in &crate::hal::platform::VIRTIO_DISKS {
kvmmap(
pagetable,
*virtio_disk_addr,
*virtio_disk_addr,
PAGE_SIZE,
PTE_R | PTE_W,
);
}
// PLIC // PLIC
kvmmap(pagetable, PLIC, PLIC, 0x400000, PTE_R | PTE_W); kvmmap(pagetable, PLIC, PLIC, 0x400000, PTE_R | PTE_W);
@ -119,12 +127,12 @@ pub unsafe fn kvminit() {
/// Switch hardware pagetable register to the kernel's pagetable and enable paging. /// Switch hardware pagetable register to the kernel's pagetable and enable paging.
pub unsafe fn kvminithart() { pub unsafe fn kvminithart() {
// Wait for any previous writes to the pagetable memory to finish. // Wait for any previous writes to the pagetable memory to finish.
arch::mem::flush_cached_pages(); flush_cached_pages();
asm::w_satp(make_satp(KERNEL_PAGETABLE)); asm::w_satp(make_satp(KERNEL_PAGETABLE));
// Flush stale entries from the TLB. // Flush stale entries from the TLB.
arch::mem::flush_cached_pages(); flush_cached_pages();
} }
/// Return the address of the PTE in pagetable /// Return the address of the PTE in pagetable

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@ -0,0 +1,8 @@
//! Device drivers and hardware implementations.
pub mod ramdisk;
pub mod uart;
pub mod virtio_disk;
#[cfg(target_arch = "riscv64")]
pub mod riscv;

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@ -1,8 +1,11 @@
use super::{asm, MIE_MTIE, MSTATUS_MIE}; use crate::{
use crate::NCPU; hal::arch::riscv::{asm, MIE_MTIE, MSTATUS_MIE},
NCPU,
};
use core::ptr::addr_of; use core::ptr::addr_of;
// Core Local Interrupter (CLINT), which contains the timer. // Core Local Interrupter (CLINT), which contains the timer.
// I'm pretty sure the CLINT address is standardized to this location.
pub const CLINT: usize = 0x2000000; pub const CLINT: usize = 0x2000000;
const CLINT_MTIME: usize = CLINT + 0xbff8; const CLINT_MTIME: usize = CLINT + 0xbff8;

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@ -0,0 +1,2 @@
pub mod clint;
pub mod plic;

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@ -1,13 +1,15 @@
//! The RISC-V Platform Level Interrupt Controller (PLIC) //! The RISC-V Platform Level Interrupt Controller (PLIC)
use super::hardware::VIRTIO0_IRQ; use crate::hal::platform::VIRTIO0_IRQ;
use crate::proc::cpu::Cpu; use crate::proc::cpu::Cpu;
// QEMU puts platform-level interrupt controller (PLIC) here. // (VIRTIO0_IRQ, VIRTIO0_IRQ_ADDR)
pub const PLIC: usize = 0x0c000000; const VIRTIO0_IRQ_ADDR: usize = PLIC + VIRTIO0_IRQ * 4;
pub use crate::hal::platform::PLIC_BASE_ADDR as PLIC;
use crate::uprintln;
const PLIC_PRIORITY: usize = PLIC; const PLIC_PRIORITY: usize = PLIC;
const PLIC_PENDING: usize = PLIC + 0x1000; const PLIC_PENDING: usize = PLIC + 0x1000;
const VIRTIO0_IRQ_ADDR: usize = PLIC + VIRTIO0_IRQ * 4;
/// Get a pointer to the CPU-specific machine-mode enable register. /// Get a pointer to the CPU-specific machine-mode enable register.
fn plic_menable(hartid: usize) -> *mut u32 { fn plic_menable(hartid: usize) -> *mut u32 {
@ -36,10 +38,12 @@ fn plic_sclaim(hartid: usize) -> *mut u32 {
pub unsafe fn plicinit() { pub unsafe fn plicinit() {
// Set desired IRQ priorities non-zero (otherwise disabled). // Set desired IRQ priorities non-zero (otherwise disabled).
for (uart_irq, _) in &crate::hardware::UARTS { for (uart_irq, _) in &crate::hal::platform::UARTS {
*((PLIC + uart_irq * 4) as *mut u32) = 1; *((PLIC + uart_irq * 4) as *mut u32) = 1;
} }
*(VIRTIO0_IRQ_ADDR as *mut u32) = 1; for (virtio_disk_irq, _) in &crate::hal::platform::VIRTIO_DISKS {
*((PLIC + virtio_disk_irq * 4) as *mut u32) = 1;
}
} }
pub unsafe fn plicinithart() { pub unsafe fn plicinithart() {
@ -48,9 +52,12 @@ pub unsafe fn plicinithart() {
// Set enable bits for this hart's S-mode // Set enable bits for this hart's S-mode
// for the UART and VIRTIO disk. // for the UART and VIRTIO disk.
let mut enable_bits = 0; let mut enable_bits = 0;
for (uart_irq, _) in &crate::hardware::UARTS { for (uart_irq, _) in &crate::hal::platform::UARTS {
enable_bits |= 1 << uart_irq; enable_bits |= 1 << uart_irq;
} }
// for (virtio_disk_irq, _) in &crate::hal::platform::VIRTIO_DISKS {
// enable_bits |= 1 << virtio_disk_irq;
// }
enable_bits |= 1 << VIRTIO0_IRQ; enable_bits |= 1 << VIRTIO0_IRQ;
*plic_senable(hart) = enable_bits; *plic_senable(hart) = enable_bits;

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@ -2,8 +2,8 @@
#![allow(non_upper_case_globals)] #![allow(non_upper_case_globals)]
use crate::{ use crate::{
arch::trap::InterruptBlocker,
console::consoleintr, console::consoleintr,
hal::arch::trap::InterruptBlocker,
proc::scheduler::wakeup, proc::scheduler::wakeup,
queue::Queue, queue::Queue,
sync::mutex::{Mutex, MutexGuard}, sync::mutex::{Mutex, MutexGuard},

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@ -0,0 +1,3 @@
pub mod arch;
pub mod hardware;
pub mod platform;

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@ -0,0 +1 @@
// TODO

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@ -0,0 +1,11 @@
#[cfg(feature = "milk-v")]
mod milk_v;
#[cfg(feature = "milk-v")]
pub use milk_v::*;
#[cfg(feature = "qemu-riscv64")]
mod qemu_riscv64;
#[cfg(feature = "qemu-riscv64")]
pub use qemu_riscv64::*;
#[cfg(not(any(feature = "milk-v", feature = "qemu-riscv64")))]
compile_error!("a platform must be selected");

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@ -0,0 +1,23 @@
use crate::hal::hardware::uart::BufferedUart;
pub static DIRECT_MAPPED_PAGES: [usize; 1] = [QEMU_POWER];
// Devices: (IRQ, driver)
pub static UARTS: [(usize, BufferedUart); 1] = [(10, BufferedUart::new(0x1000_0000))];
pub static VIRTIO_DISKS: [(usize, usize); 1] = [(1, 0x10001000)];
// Virtio MMIO interface
pub const VIRTIO0: usize = 0x10001000;
pub const VIRTIO0_IRQ: usize = 1;
// Platform Interrupt Controller location
pub const PLIC_BASE_ADDR: usize = 0x0c000000;
/// QEMU test interface. Used for power off and on.
const QEMU_POWER: usize = 0x100000;
pub unsafe fn shutdown() -> ! {
let qemu_power = QEMU_POWER as *mut u32;
qemu_power.write_volatile(0x5555u32);
unreachable!();
}

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@ -1,9 +0,0 @@
//! Device drivers and hardware implementations.
pub mod ramdisk;
pub mod uart;
pub mod virtio_disk;
use uart::BufferedUart;
pub static UARTS: [(usize, BufferedUart); 1] = [(10, BufferedUart::new(0x1000_0000))];

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@ -1,6 +1,6 @@
use crate::{ use crate::{
arch::virtual_memory::{copyin, copyout},
fs::file::{filealloc, fileclose, File, FileType}, fs::file::{filealloc, fileclose, File, FileType},
hal::arch::virtual_memory::{copyin, copyout},
mem::kalloc::{kalloc, kfree}, mem::kalloc::{kalloc, kfree},
proc::{process::Process, scheduler::wakeup}, proc::{process::Process, scheduler::wakeup},
sync::spinlock::Spinlock, sync::spinlock::Spinlock,

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@ -9,10 +9,10 @@
extern crate alloc; extern crate alloc;
extern crate core; extern crate core;
mod arch; mod hal;
mod console; mod console;
mod fs; mod fs;
mod hardware;
mod io; mod io;
mod mem; mod mem;
mod proc; mod proc;
@ -64,24 +64,24 @@ pub unsafe fn main() -> ! {
console::consoleinit(); console::consoleinit();
mem::kalloc::kinit(); mem::kalloc::kinit();
println!("\nxv6 kernel is booting"); println!("\nxv6 kernel is booting");
arch::virtual_memory::init(); hal::arch::virtual_memory::init();
arch::virtual_memory::inithart(); hal::arch::virtual_memory::inithart();
proc::process::procinit(); proc::process::procinit();
arch::trap::inithart(); hal::arch::trap::inithart();
arch::interrupt::init(); hal::arch::interrupt::init();
arch::interrupt::inithart(); hal::arch::interrupt::inithart();
io::bio::binit(); io::bio::binit();
fs::inode::iinit(); fs::inode::iinit();
hardware::virtio_disk::virtio_disk_init(); hal::hardware::virtio_disk::virtio_disk_init();
proc::process::userinit(); proc::process::userinit();
STARTED = true; STARTED = true;
} else { } else {
while !STARTED { while !STARTED {
core::hint::spin_loop(); core::hint::spin_loop();
} }
arch::virtual_memory::inithart(); hal::arch::virtual_memory::inithart();
arch::trap::inithart(); hal::arch::trap::inithart();
arch::interrupt::inithart(); hal::arch::interrupt::inithart();
} }
proc::scheduler::scheduler(); proc::scheduler::scheduler();
} }

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@ -3,7 +3,7 @@
//! and pipe buffers. Allocates whole 4096-byte pages. //! and pipe buffers. Allocates whole 4096-byte pages.
use crate::{ use crate::{
arch::mem::{round_up_page, PAGE_SIZE, PHYSICAL_END}, hal::arch::mem::{round_up_page, PAGE_SIZE, PHYSICAL_END},
mem::memset, mem::memset,
sync::spinlock::Spinlock, sync::spinlock::Spinlock,
}; };

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@ -28,7 +28,7 @@ impl Cpu {
/// to prevent race with process being moved /// to prevent race with process being moved
/// to a different CPU. /// to a different CPU.
pub fn current_id() -> usize { pub fn current_id() -> usize {
crate::arch::cpu::cpu_id() crate::hal::arch::cpu::cpu_id()
} }
/// Return this CPU's cpu struct. /// Return this CPU's cpu struct.
/// Interrupts must be disabled. /// Interrupts must be disabled.

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@ -7,14 +7,6 @@ use super::{
trapframe::Trapframe, trapframe::Trapframe,
}; };
use crate::{ use crate::{
arch::{
mem::{kstack, Pagetable, PAGE_SIZE, PTE_R, PTE_W, PTE_X, TRAMPOLINE, TRAPFRAME},
trap::{usertrapret, InterruptBlocker},
virtual_memory::{
copyout, mappages, uvmalloc, uvmcopy, uvmcreate, uvmdealloc, uvmfirst, uvmfree,
uvmunmap,
},
},
fs::{ fs::{
file::{fileclose, filedup, File}, file::{fileclose, filedup, File},
fsinit, fsinit,
@ -22,6 +14,14 @@ use crate::{
log::LogOperation, log::LogOperation,
FS_INITIALIZED, FS_INITIALIZED,
}, },
hal::arch::{
mem::{kstack, Pagetable, PAGE_SIZE, PTE_R, PTE_W, PTE_X, TRAMPOLINE, TRAPFRAME},
trap::{usertrapret, InterruptBlocker},
virtual_memory::{
copyout, mappages, uvmalloc, uvmcopy, uvmcreate, uvmdealloc, uvmfirst, uvmfree,
uvmunmap,
},
},
mem::{ mem::{
kalloc::{kalloc, kfree}, kalloc::{kalloc, kfree},
memset, memset,

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@ -4,8 +4,8 @@ use super::{
process::{Process, ProcessState, PROCESSES}, process::{Process, ProcessState, PROCESSES},
}; };
use crate::{ use crate::{
arch,
console::printf::println, console::printf::println,
hal::arch,
sync::spinlock::{Spinlock, SpinlockGuard}, sync::spinlock::{Spinlock, SpinlockGuard},
}; };
use core::{ use core::{

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@ -29,7 +29,7 @@ impl Lock {
match lock_strategy { match lock_strategy {
LockStrategy::Spin => { LockStrategy::Spin => {
crate::arch::trap::push_intr_off(); crate::hal::arch::trap::push_intr_off();
while self.locked.swap(true, Ordering::Acquire) { while self.locked.swap(true, Ordering::Acquire) {
core::hint::spin_loop(); core::hint::spin_loop();
@ -63,7 +63,7 @@ impl Lock {
match lock_strategy { match lock_strategy {
LockStrategy::Spin => { LockStrategy::Spin => {
crate::arch::trap::pop_intr_off(); crate::hal::arch::trap::pop_intr_off();
} }
LockStrategy::Sleep => { LockStrategy::Sleep => {
wakeup(addr_of!(*self).cast_mut().cast()); wakeup(addr_of!(*self).cast_mut().cast());

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@ -1,5 +1,5 @@
use crate::{ use crate::{
arch::trap::{pop_intr_off, push_intr_off}, hal::arch::trap::{pop_intr_off, push_intr_off},
proc::{ proc::{
process::{Process, ProcessState}, process::{Process, ProcessState},
scheduler::sched, scheduler::sched,

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@ -1,15 +1,17 @@
use crate::{ use crate::{
arch::{
clock::CLOCK_TICKS,
power::shutdown,
virtual_memory::{copyin, copyinstr},
},
fs::{ fs::{
file::{self, File}, file::{self, File},
inode::{ilock, iput, iunlock, namei}, inode::{ilock, iput, iunlock, namei},
log::LogOperation, log::LogOperation,
stat::KIND_DIR, stat::KIND_DIR,
}, },
hal::{
arch::{
clock::CLOCK_TICKS,
virtual_memory::{copyin, copyinstr},
},
platform::shutdown,
},
println, println,
proc::process::Process, proc::process::Process,
string::strlen, string::strlen,