Implement all asm instructions in riscv.h
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709ec3a50f
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GPG Key ID:
D7A048C454CB7054
@ -1,190 +0,0 @@
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use core::arch::asm;
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pub type Pte = u64;
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pub type Pagetable = *mut [Pte; 512];
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/// Previous mode
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pub const MSTATUS_MPP_MASK: u64 = 3 << 11;
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pub const MSTATUS_MPP_M: u64 = 3 << 11;
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pub const MSTATUS_MPP_S: u64 = 1 << 11;
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pub const MSTATUS_MPP_U: u64 = 0 << 11;
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/// Machine-mode interrupt enable.
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pub const MSTATUS_MIE: u64 = 1 << 3;
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/// Previous mode: 1 = Supervisor, 0 = User
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pub const SSTATUS_SPP: u64 = 1 << 8;
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/// Supervisor Previous Interrupt Enable
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pub const SSTATUS_SPIE: u64 = 1 << 5;
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/// User Previous Interrupt Enable
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pub const SSTATUS_UPIE: u64 = 1 << 4;
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/// Supervisor Interrupt Enable
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pub const SSTATUS_SIE: u64 = 1 << 1;
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/// User Interrupt Enable
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pub const SSTATUS_UIE: u64 = 1 << 0;
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/// Supervisor External Interrupt Enable
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pub const SIE_SEIE: u64 = 1 << 9;
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/// Supervisor Timer Interrupt Enable
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pub const SIE_STIE: u64 = 1 << 5;
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/// Supervisor Software Interrupt Enable
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pub const SIE_SSIE: u64 = 1 << 1;
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/// Machine-mode External Interrupt Enable
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pub const MIE_MEIE: u64 = 1 << 11;
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/// Machine-mode Timer Interrupt Enable
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pub const MIE_MTIE: u64 = 1 << 7;
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/// Machine-mode Software Interrupt Enable
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pub const MIE_MSIE: u64 = 1 << 3;
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pub const SATP_SV39: u64 = 8 << 60;
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/// Bytes per page
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pub const PGSIZE: u64 = 4096;
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/// Bits of offset within a page
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pub const PGSHIFT: u64 = 12;
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pub const PTE_V: u64 = 1 << 0;
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pub const PTE_R: u64 = 1 << 1;
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pub const PTE_W: u64 = 1 << 2;
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pub const PTE_X: u64 = 1 << 3;
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pub const PTE_U: u64 = 1 << 4;
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/// Which hart (core) is this?
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#[inline(always)]
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pub unsafe fn r_mhartid() -> u64 {
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let x: u64;
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asm!("csrr {}, mhartid", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn r_tp() -> u64 {
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let x: u64;
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asm!("mv {}, tp", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn w_sstatus(x: u64) {
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asm!("csrw sstatus, {}", in(reg) x);
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}
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#[inline(always)]
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pub unsafe fn r_sstatus() -> u64 {
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let x: u64;
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asm!("csrr {}, sstatus", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn intr_on() {
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w_sstatus(r_sstatus() | SSTATUS_SIE);
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}
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#[inline(always)]
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pub unsafe fn intr_off() {
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w_sstatus(r_sstatus() & !SSTATUS_SIE);
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}
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#[inline(always)]
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pub unsafe fn intr_get() -> i32 {
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if (r_sstatus() & SSTATUS_SIE) > 0 {
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1
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} else {
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0
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}
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}
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extern "C" {
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/// Which hart (core) is this?
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pub fn rv_r_mhartid() -> u64;
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// Machine Status Register, mstatus
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pub fn r_mstatus() -> u64;
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pub fn w_mstatus(x: u64);
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// Machine Exception Program Counter
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// MEPC holds the instruction address to which a return from exception will go.
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pub fn w_mepc(x: u64);
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// Supervisor Status Register, sstatus
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pub fn rv_r_sstatus() -> u64;
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pub fn rv_w_sstatus(x: u64);
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// Supervisor Interrupt Pending
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pub fn r_sip() -> u64;
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pub fn w_sip(x: u64);
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// Supervisor Interrupt Enable
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pub fn r_sie() -> u64;
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pub fn w_sie(x: u64);
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// Machine-mode Interrupt Enable
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pub fn r_mie() -> u64;
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pub fn w_mie(x: u64);
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// Supervisor Exception Program Counter
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// SEPC holds the instruction address to which a return from exception will go.
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pub fn r_sepc() -> u64;
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pub fn w_sepc(x: u64);
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// Machine Exception Deletgation
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pub fn r_medeleg() -> u64;
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pub fn w_medeleg(x: u64);
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// Machine Interrupt Deletgation
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pub fn r_mideleg() -> u64;
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pub fn w_mideleg(x: u64);
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// Supervisor Trap-Vector Base Address
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pub fn r_stvec() -> u64;
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pub fn w_stvec(x: u64);
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// Machine-mode Interrupt Vector
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pub fn w_mtvec(x: u64);
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// Physical Memory Protection
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pub fn w_pmpcfg0(x: u64);
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pub fn w_pmpaddr0(x: u64);
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// Supervisor Address Translation and Protection
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// SATP holds the address of the page table.
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pub fn r_satp() -> u64;
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pub fn w_satp(x: u64);
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pub fn w_mscratch(x: u64);
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// Supervisor Trap Cause
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pub fn r_scause() -> u64;
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// Supervisor Trap Value
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pub fn r_stval() -> u64;
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// Machine-mode Counter-Enable
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pub fn r_mcounteren() -> u64;
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pub fn w_mcounteren(x: u64);
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// Machine-mode cycle counter
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pub fn r_time() -> u64;
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// /// Enable device interrupts
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// pub fn intr_on();
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// /// Disable device interrupts
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// pub fn intr_off();
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// // Are device interrupts enabled?
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// pub fn intr_get() -> i32;
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pub fn r_sp() -> u64;
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// Read and write TP (thread pointer), which xv6 uses
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// to hold this core's hartid, the index into cpus[].
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// pub fn rv_r_tp() -> u64;
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pub fn w_tp(x: u64);
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pub fn r_ra() -> u64;
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/// Flush the TLB.
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pub fn sfence_vma();
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}
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254
kernel/rustkernel/src/riscv/asm.rs
Normal file
254
kernel/rustkernel/src/riscv/asm.rs
Normal file
@ -0,0 +1,254 @@
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use super::*;
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use core::arch::asm;
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/// Which hart (core) is this?
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#[inline(always)]
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pub unsafe fn r_mhartid() -> u64 {
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let x: u64;
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asm!("csrr {}, mhartid", out(reg) x);
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x
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}
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// Machine Status Register, mstatus
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#[inline(always)]
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pub unsafe fn r_mstatus() -> u64 {
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let x: u64;
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asm!("csrr {}, mstatus", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn w_mstatus(x: u64) {
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asm!("csrw mstatus, {}", in(reg) x);
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}
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// Machine Exception Program Counter
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// MEPC holds the instruction address to which a return from exception will go.
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#[inline(always)]
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pub unsafe fn w_mepc(x: u64) {
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asm!("csrw mepc, {}", in(reg) x);
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}
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// Supervisor Status Register, sstatus
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#[inline(always)]
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pub unsafe fn r_sstatus() -> u64 {
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let x: u64;
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asm!("csrr {}, sstatus", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn w_sstatus(x: u64) {
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asm!("csrw sstatus, {}", in(reg) x);
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}
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// Supervisor Interrupt Pending
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#[inline(always)]
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pub unsafe fn r_sip() -> u64 {
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let x: u64;
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asm!("csrr {}, sip", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn w_sip(x: u64) {
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asm!("csrw sip, {}", in(reg) x);
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}
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// Supervisor Interrupt Enable
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#[inline(always)]
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pub unsafe fn r_sie() -> u64 {
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let x: u64;
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asm!("csrr {}, sie", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn w_sie(x: u64) {
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asm!("csrw sie, {}", in(reg) x);
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}
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// Machine-mode Interrupt Enable
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#[inline(always)]
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pub unsafe fn r_mie() -> u64 {
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let x: u64;
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asm!("csrr {}, mie", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn w_mie(x: u64) {
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asm!("csrw mie, {}", in(reg) x);
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}
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// Supervisor Exception Program Counter
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// SEPC holds the instruction address to which a return from exception will go.
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#[inline(always)]
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pub unsafe fn r_sepc() -> u64 {
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let x: u64;
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asm!("csrr {}, sepc", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn w_sepc(x: u64) {
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asm!("csrw sepc, {}", in(reg) x);
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}
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// Machine Exception Delegation
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#[inline(always)]
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pub unsafe fn r_medeleg() -> u64 {
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let x: u64;
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asm!("csrr {}, medeleg", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn w_medeleg(x: u64) {
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asm!("csrw medeleg, {}", in(reg) x);
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}
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// Machine Interrupt Delegation
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#[inline(always)]
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pub unsafe fn r_mideleg() -> u64 {
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let x: u64;
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asm!("csrr {}, mideleg", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn w_mideleg(x: u64) {
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asm!("csrw mideleg, {}", in(reg) x);
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}
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// Supervisor Trap-Vector Base Address
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#[inline(always)]
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pub unsafe fn r_stvec() -> u64 {
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let x: u64;
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asm!("csrr {}, stvec", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn w_stvec(x: u64) {
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asm!("csrw stvec, {}", in(reg) x);
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}
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// Machine-mode Interrupt Vector
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#[inline(always)]
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pub unsafe fn w_mtvec(x: u64) {
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asm!("csrw mtvec, {}", in(reg) x);
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}
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// Physical Memory Protection
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#[inline(always)]
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pub unsafe fn w_pmpcfg0(x: u64) {
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asm!("csrw pmpcfg0, {}", in(reg) x);
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}
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#[inline(always)]
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pub unsafe fn w_pmpaddr0(x: u64) {
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asm!("csrw pmpaddr0, {}", in(reg) x);
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}
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// Supervisor Address Translation and Protection
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// SATP holds the address of the page table.
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#[inline(always)]
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pub unsafe fn r_satp() -> u64 {
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let x: u64;
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asm!("csrr {}, satp", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn w_satp(x: u64) {
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asm!("csrw satp, {}", in(reg) x);
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}
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#[inline(always)]
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pub unsafe fn w_mscratch(x: u64) {
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asm!("csrw mscratch, {}", in(reg) x);
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}
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// Supervisor Trap Cause
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#[inline(always)]
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pub unsafe fn r_scause() -> u64 {
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let x: u64;
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asm!("csrr {}, scause", out(reg) x);
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x
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}
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// Supervisor Trap Value
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#[inline(always)]
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pub unsafe fn r_stval() -> u64 {
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let x: u64;
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asm!("csrr {}, stval", out(reg) x);
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x
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}
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// Machine-mode Counter-Enable
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#[inline(always)]
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pub unsafe fn r_mcounteren() -> u64 {
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let x: u64;
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asm!("csrr {}, mcounteren", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn w_mcounteren(x: u64) {
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asm!("csrw mcounteren, {}", in(reg) x);
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}
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// Machine-mode cycle counter
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#[inline(always)]
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pub unsafe fn r_time() -> u64 {
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let x: u64;
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asm!("csrr {}, time", out(reg) x);
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x
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}
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// Enable device interrupts
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#[inline(always)]
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pub unsafe fn intr_on() {
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w_sstatus(r_sstatus() | SSTATUS_SIE);
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}
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// Disable device interrupts
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#[inline(always)]
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pub unsafe fn intr_off() {
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w_sstatus(r_sstatus() & !SSTATUS_SIE);
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}
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// Are device interrupts enabled?
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#[inline(always)]
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pub unsafe fn intr_get() -> i32 {
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if (r_sstatus() & SSTATUS_SIE) > 0 {
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1
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} else {
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0
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}
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}
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#[inline(always)]
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pub unsafe fn r_sp() -> u64 {
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let x: u64;
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asm!("mv {}, sp", out(reg) x);
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x
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}
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// Read and write TP (thread pointer), which xv6 uses
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// to hold this core's hartid, the index into cpus[].
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// pub fn rv_r_tp() -> u64;
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#[inline(always)]
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pub unsafe fn r_tp() -> u64 {
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let x: u64;
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asm!("mv {}, tp", out(reg) x);
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x
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}
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#[inline(always)]
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pub unsafe fn w_tp(x: u64) {
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asm!("mv tp, {}", in(reg) x);
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}
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#[inline(always)]
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pub unsafe fn r_ra() -> u64 {
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let x: u64;
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asm!("mv {}, ra", out(reg) x);
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x
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}
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// Flush the TLB.
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#[inline(always)]
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pub unsafe fn sfence_vma() {
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// The "zero, zero" means flush all TLB entries.
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asm!("sfence.vma zero, zero");
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}
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52
kernel/rustkernel/src/riscv/mod.rs
Normal file
52
kernel/rustkernel/src/riscv/mod.rs
Normal file
@ -0,0 +1,52 @@
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pub mod asm;
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pub use asm::*;
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pub type Pte = u64;
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pub type Pagetable = *mut [Pte; 512];
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/// Previous mode
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pub const MSTATUS_MPP_MASK: u64 = 3 << 11;
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pub const MSTATUS_MPP_M: u64 = 3 << 11;
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pub const MSTATUS_MPP_S: u64 = 1 << 11;
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pub const MSTATUS_MPP_U: u64 = 0 << 11;
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/// Machine-mode interrupt enable.
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pub const MSTATUS_MIE: u64 = 1 << 3;
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/// Previous mode: 1 = Supervisor, 0 = User
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pub const SSTATUS_SPP: u64 = 1 << 8;
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/// Supervisor Previous Interrupt Enable
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pub const SSTATUS_SPIE: u64 = 1 << 5;
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/// User Previous Interrupt Enable
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pub const SSTATUS_UPIE: u64 = 1 << 4;
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/// Supervisor Interrupt Enable
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pub const SSTATUS_SIE: u64 = 1 << 1;
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/// User Interrupt Enable
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pub const SSTATUS_UIE: u64 = 1 << 0;
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/// Supervisor External Interrupt Enable
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pub const SIE_SEIE: u64 = 1 << 9;
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/// Supervisor Timer Interrupt Enable
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pub const SIE_STIE: u64 = 1 << 5;
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/// Supervisor Software Interrupt Enable
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pub const SIE_SSIE: u64 = 1 << 1;
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|
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/// Machine-mode External Interrupt Enable
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pub const MIE_MEIE: u64 = 1 << 11;
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/// Machine-mode Timer Interrupt Enable
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pub const MIE_MTIE: u64 = 1 << 7;
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/// Machine-mode Software Interrupt Enable
|
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pub const MIE_MSIE: u64 = 1 << 3;
|
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|
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pub const SATP_SV39: u64 = 8 << 60;
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|
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/// Bytes per page
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||||
pub const PGSIZE: u64 = 4096;
|
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/// Bits of offset within a page
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pub const PGSHIFT: u64 = 12;
|
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|
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pub const PTE_V: u64 = 1 << 0;
|
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pub const PTE_R: u64 = 1 << 1;
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pub const PTE_W: u64 = 1 << 2;
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pub const PTE_X: u64 = 1 << 3;
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||||
pub const PTE_U: u64 = 1 << 4;
|
||||
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