move riscv module into arch module
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6d9a0a34e1
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ac33c19b5f
@ -147,10 +147,7 @@ int fetchaddr(uint64, uint64*);
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void syscall();
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void syscall();
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// trap.c
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// trap.c
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extern uint ticks;
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void trapinit(void);
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void trapinithart(void);
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void trapinithart(void);
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extern struct spinlock tickslock;
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void usertrapret(void);
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void usertrapret(void);
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void uartintr(void);
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void uartintr(void);
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1
kernel/rustkernel/src/arch/mod.rs
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1
kernel/rustkernel/src/arch/mod.rs
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@ -0,0 +1 @@
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pub mod riscv;
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@ -2,7 +2,7 @@
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use crate::{
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use crate::{
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proc::cpuid,
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proc::cpuid,
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riscv::{plic_sclaim, plic_senable, plic_spriority, PLIC, UART0_IRQ, VIRTIO0_IRQ},
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arch::riscv::{plic_sclaim, plic_senable, plic_spriority, PLIC, UART0_IRQ, VIRTIO0_IRQ},
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};
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};
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#[no_mangle]
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#[no_mangle]
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@ -24,7 +24,7 @@ const LSR_RX_READY: u8 = 1 << 0;
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/// THR can accept another character to send
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/// THR can accept another character to send
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const LSR_TX_IDLE: u8 = 1 << 5;
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const LSR_TX_IDLE: u8 = 1 << 5;
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pub static UART0: Uart = Uart::new(crate::riscv::memlayout::UART0);
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pub static UART0: Uart = Uart::new(crate::arch::riscv::memlayout::UART0);
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enum Register {
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enum Register {
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ReceiveHolding,
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ReceiveHolding,
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@ -14,7 +14,7 @@ pub mod io;
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pub mod mem;
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pub mod mem;
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pub mod proc;
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pub mod proc;
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pub mod queue;
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pub mod queue;
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pub(crate) mod riscv;
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pub(crate) mod arch;
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pub mod start;
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pub mod start;
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pub mod string;
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pub mod string;
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pub mod sync;
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pub mod sync;
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@ -66,8 +66,8 @@ pub unsafe extern "C" fn main() -> ! {
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mem::virtual_memory::kvminithart();
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mem::virtual_memory::kvminithart();
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proc::procinit();
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proc::procinit();
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trap::trapinithart();
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trap::trapinithart();
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riscv::plic::plicinit();
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arch::riscv::plic::plicinit();
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riscv::plic::plicinithart();
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arch::riscv::plic::plicinithart();
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io::bio::binit();
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io::bio::binit();
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fs::iinit();
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fs::iinit();
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fs::file::fileinit();
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fs::file::fileinit();
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@ -80,7 +80,7 @@ pub unsafe extern "C" fn main() -> ! {
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}
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}
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mem::virtual_memory::kvminithart();
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mem::virtual_memory::kvminithart();
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trap::trapinithart();
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trap::trapinithart();
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riscv::plic::plicinithart();
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arch::riscv::plic::plicinithart();
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}
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}
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proc::scheduler();
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proc::scheduler();
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@ -4,7 +4,7 @@
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use crate::{
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use crate::{
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mem::memset,
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mem::memset,
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riscv::{memlayout::PHYSTOP, pg_round_up, PGSIZE},
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arch::riscv::{memlayout::PHYSTOP, pg_round_up, PGSIZE},
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sync::spinlock::Spinlock,
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sync::spinlock::Spinlock,
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};
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};
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use core::ptr::{addr_of_mut, null_mut};
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use core::ptr::{addr_of_mut, null_mut};
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@ -4,7 +4,7 @@ use crate::{
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memmove, memset,
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memmove, memset,
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},
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},
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proc::proc_mapstacks,
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proc::proc_mapstacks,
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riscv::{
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arch::riscv::{
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memlayout::{KERNBASE, PHYSTOP, TRAMPOLINE},
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memlayout::{KERNBASE, PHYSTOP, TRAMPOLINE},
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*,
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*,
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},
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},
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@ -2,7 +2,7 @@
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use crate::{
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use crate::{
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mem::kalloc::kfree,
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mem::kalloc::kfree,
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riscv::{self, Pagetable, PTE_W},
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arch::riscv::{Pagetable, PTE_W, intr_get, r_tp},
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sync::spinlock::{Spinlock, SpinlockGuard},
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sync::spinlock::{Spinlock, SpinlockGuard},
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};
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};
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use core::{
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use core::{
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@ -226,7 +226,7 @@ pub struct Proc {
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/// to a different CPU.
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/// to a different CPU.
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#[no_mangle]
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#[no_mangle]
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pub unsafe extern "C" fn cpuid() -> i32 {
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pub unsafe extern "C" fn cpuid() -> i32 {
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riscv::r_tp() as i32
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r_tp() as i32
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}
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}
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/// Return this CPU's cpu struct.
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/// Return this CPU's cpu struct.
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@ -331,7 +331,7 @@ pub unsafe extern "C" fn sched() {
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panic!("sched locks");
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panic!("sched locks");
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} else if (*p).state == ProcState::Running {
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} else if (*p).state == ProcState::Running {
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panic!("sched running");
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panic!("sched running");
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} else if riscv::intr_get() > 0 {
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} else if intr_get() > 0 {
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panic!("sched interruptible");
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panic!("sched interruptible");
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}
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}
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@ -1,4 +1,4 @@
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use crate::{main, riscv::*, NCPU};
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use crate::{main, arch::riscv::*, NCPU};
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use core::{arch::asm, ptr::addr_of};
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use core::{arch::asm, ptr::addr_of};
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extern "C" {
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extern "C" {
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@ -2,7 +2,7 @@ use crate::{
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mem::virtual_memory::{copyin, copyinstr},
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mem::virtual_memory::{copyin, copyinstr},
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println,
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println,
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proc::{self, myproc},
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proc::{self, myproc},
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riscv::memlayout::QEMU_POWER,
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arch::riscv::memlayout::QEMU_POWER,
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string::strlen,
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string::strlen,
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trap::CLOCK_TICKS,
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trap::CLOCK_TICKS,
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};
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};
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@ -1,7 +1,7 @@
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use crate::{
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use crate::{
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println,
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println,
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proc::{cpuid, exit, killed, mycpu, myproc, r#yield, setkilled, wakeup, ProcState},
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proc::{cpuid, exit, killed, mycpu, myproc, r#yield, setkilled, wakeup, ProcState},
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riscv::*,
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arch::riscv::*,
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sync::mutex::Mutex,
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sync::mutex::Mutex,
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syscall::syscall,
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syscall::syscall,
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};
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};
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@ -272,10 +272,10 @@ pub unsafe extern "C" fn usertrap() {
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#[no_mangle]
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#[no_mangle]
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pub unsafe extern "C" fn push_intr_off() {
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pub unsafe extern "C" fn push_intr_off() {
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let old = crate::riscv::intr_get();
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let old = intr_get();
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let cpu = mycpu();
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let cpu = mycpu();
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crate::riscv::intr_off();
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intr_off();
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if (*cpu).interrupt_disable_layers == 0 {
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if (*cpu).interrupt_disable_layers == 0 {
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(*cpu).previous_interrupts_enabled = old;
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(*cpu).previous_interrupts_enabled = old;
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}
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}
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@ -285,7 +285,7 @@ pub unsafe extern "C" fn push_intr_off() {
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pub unsafe extern "C" fn pop_intr_off() {
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pub unsafe extern "C" fn pop_intr_off() {
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let cpu = mycpu();
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let cpu = mycpu();
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if crate::riscv::intr_get() == 1 {
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if intr_get() == 1 {
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// crate::panic_byte(b'0');
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// crate::panic_byte(b'0');
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panic!("pop_intr_off - interruptible");
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panic!("pop_intr_off - interruptible");
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} else if (*cpu).interrupt_disable_layers < 1 {
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} else if (*cpu).interrupt_disable_layers < 1 {
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@ -296,6 +296,6 @@ pub unsafe extern "C" fn pop_intr_off() {
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(*cpu).interrupt_disable_layers -= 1;
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(*cpu).interrupt_disable_layers -= 1;
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if (*cpu).interrupt_disable_layers == 0 && (*cpu).previous_interrupts_enabled == 1 {
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if (*cpu).interrupt_disable_layers == 0 && (*cpu).previous_interrupts_enabled == 1 {
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crate::riscv::intr_on();
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intr_on();
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}
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}
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}
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}
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