move riscv module into arch module

kernel/defs.h

@@ -147,10 +147,7 @@ int             fetchaddr(uint64, uint64*);
 void            syscall();
 
 // trap.c
-extern uint     ticks;
+void trapinithart(void);
-void            trapinit(void);
-void            trapinithart(void);
-extern struct spinlock tickslock;
 void            usertrapret(void);
 void            uartintr(void);
 

kernel/rustkernel/src/arch/mod.rs

@@ -0,0 +1 @@
+pub mod riscv;

kernel/rustkernel/src/arch/riscv/plic.rs

@@ -2,7 +2,7 @@
 
 use crate::{
     proc::cpuid,
-    riscv::{plic_sclaim, plic_senable, plic_spriority, PLIC, UART0_IRQ, VIRTIO0_IRQ},
+    arch::riscv::{plic_sclaim, plic_senable, plic_spriority, PLIC, UART0_IRQ, VIRTIO0_IRQ},
 };
 
 #[no_mangle]

kernel/rustkernel/src/console/uart.rs

@@ -24,7 +24,7 @@ const LSR_RX_READY: u8 = 1 << 0;
 /// THR can accept another character to send
 const LSR_TX_IDLE: u8 = 1 << 5;
 
-pub static UART0: Uart = Uart::new(crate::riscv::memlayout::UART0);
+pub static UART0: Uart = Uart::new(crate::arch::riscv::memlayout::UART0);
 
 enum Register {
     ReceiveHolding,

kernel/rustkernel/src/lib.rs

@@ -14,7 +14,7 @@ pub mod io;
 pub mod mem;
 pub mod proc;
 pub mod queue;
-pub(crate) mod riscv;
+pub(crate) mod arch;
 pub mod start;
 pub mod string;
 pub mod sync;
@@ -66,8 +66,8 @@ pub unsafe extern "C" fn main() -> ! {
         mem::virtual_memory::kvminithart();
         proc::procinit();
         trap::trapinithart();
-        riscv::plic::plicinit();
+        arch::riscv::plic::plicinit();
-        riscv::plic::plicinithart();
+        arch::riscv::plic::plicinithart();
         io::bio::binit();
         fs::iinit();
         fs::file::fileinit();
@@ -80,7 +80,7 @@ pub unsafe extern "C" fn main() -> ! {
         }
         mem::virtual_memory::kvminithart();
         trap::trapinithart();
-        riscv::plic::plicinithart();
+        arch::riscv::plic::plicinithart();
     }
 
     proc::scheduler();

kernel/rustkernel/src/mem/kalloc.rs

@@ -4,7 +4,7 @@
 
 use crate::{
     mem::memset,
-    riscv::{memlayout::PHYSTOP, pg_round_up, PGSIZE},
+    arch::riscv::{memlayout::PHYSTOP, pg_round_up, PGSIZE},
     sync::spinlock::Spinlock,
 };
 use core::ptr::{addr_of_mut, null_mut};

kernel/rustkernel/src/mem/virtual_memory.rs

@@ -4,7 +4,7 @@ use crate::{
         memmove, memset,
     },
     proc::proc_mapstacks,
-    riscv::{
+    arch::riscv::{
         memlayout::{KERNBASE, PHYSTOP, TRAMPOLINE},
         *,
     },

kernel/rustkernel/src/proc.rs

@@ -2,7 +2,7 @@
 
 use crate::{
     mem::kalloc::kfree,
-    riscv::{self, Pagetable, PTE_W},
+    arch::riscv::{Pagetable, PTE_W, intr_get, r_tp},
     sync::spinlock::{Spinlock, SpinlockGuard},
 };
 use core::{
@@ -226,7 +226,7 @@ pub struct Proc {
 /// to a different CPU.
 #[no_mangle]
 pub unsafe extern "C" fn cpuid() -> i32 {
-    riscv::r_tp() as i32
+    r_tp() as i32
 }
 
 /// Return this CPU's cpu struct.
@@ -331,7 +331,7 @@ pub unsafe extern "C" fn sched() {
         panic!("sched locks");
     } else if (*p).state == ProcState::Running {
         panic!("sched running");
-    } else if riscv::intr_get() > 0 {
+    } else if intr_get() > 0 {
         panic!("sched interruptible");
     }
 

kernel/rustkernel/src/start.rs

@@ -1,4 +1,4 @@
-use crate::{main, riscv::*, NCPU};
+use crate::{main, arch::riscv::*, NCPU};
 use core::{arch::asm, ptr::addr_of};
 
 extern "C" {

kernel/rustkernel/src/syscall.rs

@@ -2,7 +2,7 @@ use crate::{
     mem::virtual_memory::{copyin, copyinstr},
     println,
     proc::{self, myproc},
-    riscv::memlayout::QEMU_POWER,
+    arch::riscv::memlayout::QEMU_POWER,
     string::strlen,
     trap::CLOCK_TICKS,
 };

kernel/rustkernel/src/trap.rs

@@ -1,7 +1,7 @@
 use crate::{
     println,
     proc::{cpuid, exit, killed, mycpu, myproc, r#yield, setkilled, wakeup, ProcState},
-    riscv::*,
+    arch::riscv::*,
     sync::mutex::Mutex,
     syscall::syscall,
 };
@@ -272,10 +272,10 @@ pub unsafe extern "C" fn usertrap() {
 
 #[no_mangle]
 pub unsafe extern "C" fn push_intr_off() {
-    let old = crate::riscv::intr_get();
+    let old = intr_get();
     let cpu = mycpu();
 
-    crate::riscv::intr_off();
+    intr_off();
     if (*cpu).interrupt_disable_layers == 0 {
         (*cpu).previous_interrupts_enabled = old;
     }
@@ -285,7 +285,7 @@ pub unsafe extern "C" fn push_intr_off() {
 pub unsafe extern "C" fn pop_intr_off() {
     let cpu = mycpu();
 
-    if crate::riscv::intr_get() == 1 {
+    if intr_get() == 1 {
         // crate::panic_byte(b'0');
         panic!("pop_intr_off - interruptible");
     } else if (*cpu).interrupt_disable_layers < 1 {
@@ -296,6 +296,6 @@ pub unsafe extern "C" fn pop_intr_off() {
     (*cpu).interrupt_disable_layers -= 1;
 
     if (*cpu).interrupt_disable_layers == 0 && (*cpu).previous_interrupts_enabled == 1 {
-        crate::riscv::intr_on();
+        intr_on();
     }
 }