garentyler/xv6-riscv
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Clean up project

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This commit is contained in:
Garen Tyler 2024-07-22 10:42:41 -06:00
parent 6ef3df9177
commit 999c738862
Signed by: garentyler
GPG Key ID: D7A048C454CB7054
4 changed files with 13 additions and 64 deletions
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2
Makefile
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@ -34,6 +34,8 @@ CFLAGS += -MD
CFLAGS += -mcmodel=medany
CFLAGS += -ffreestanding -fno-common -nostdlib -mno-relax
CFLAGS += -I.
CFLAGS += -march=rv64gc
CFLAGS += -mabi=lp64d
CFLAGS += $(shell $(CC) -fno-stack-protector -E -x c /dev/null >/dev/null 2>&1 && echo -fno-stack-protector)
# Disable PIE when possible (for Ubuntu 16.10 toolchain)

52
\
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@ -1,52 +0,0 @@
use crate::hal::arch::riscv::{asm, MIE_MTIE, MSTATUS_MIE};
use crate::NCPU;
use core::ptr::addr_of;
// Core Local Interrupter (CLINT), which contains the timer.
pub const CLINT: usize = 0x2000000;
const CLINT_MTIME: usize = CLINT + 0xbff8;
extern "C" {
pub fn timervec();
}
#[no_mangle]
pub static mut timer_scratch: [[u64; 5]; NCPU] = [[0u64; 5]; NCPU];
fn clint_mtimecmp(hartid: usize) -> *mut u64 {
(CLINT + 0x4000 + (8 * hartid)) as *mut u64
}
/// Arrange to receive timer interrupts.
///
/// They will arrive in machine mode at
/// at timervec in kernelvec.S,
/// which turns them into software interrupts for
/// devintr() in trap.c.
pub unsafe fn timerinit() {
// Each CPU has a separate source of timer interrupts.
let id = asm::r_mhartid() as usize;
// Ask the CLINT for a timer interrupt.
// cycles, about 1/10th second in qemu
let interval = 1_000_000u64;
*clint_mtimecmp(id) = *(CLINT_MTIME as *const u64) + interval;
// Prepare information in scratch[] for timervec.
// scratch[0..=2]: Space for timervec to save registers.
// scratch[3]: Address of CLINT MTIMECMP register.
// scratch[4]: Desired interval (in cycles) between timer interrupts.
let scratch: &mut [u64; 5] = &mut timer_scratch[id];
scratch[3] = clint_mtimecmp(id) as usize as u64;
scratch[4] = interval;
asm::w_mscratch(addr_of!(scratch[0]) as usize as u64);
// Set the machine-mode trap handler.
asm::w_mtvec(timervec as usize as u64);
// Enable machine-mode interrupts.
asm::w_mstatus(asm::r_mstatus() | MSTATUS_MIE);
// Enable machine-mode timer interrupts.
asm::w_mie(asm::r_mie() | MIE_MTIE);
}

1
kernel/rustkernel/src/hal/hardware/riscv/plic.rs
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@ -7,7 +7,6 @@ use crate::proc::cpu::Cpu;
const VIRTIO0_IRQ_ADDR: usize = PLIC + VIRTIO0_IRQ * 4;
pub use crate::hal::platform::PLIC_BASE_ADDR as PLIC;
use crate::uprintln;
const PLIC_PRIORITY: usize = PLIC;
const PLIC_PENDING: usize = PLIC + 0x1000;

22
kernel/rustkernel/src/lib.rs
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@ -3,7 +3,6 @@
#![allow(dead_code)]
#![allow(clippy::missing_safety_doc)]
#![feature(negative_impls)]
#![feature(panic_info_message)]
#![feature(str_from_raw_parts)]
extern crate alloc;
@ -23,7 +22,7 @@ mod syscall;
use crate::{proc::cpu::Cpu, sync::mutex::Mutex};
use core::{
ffi::{c_char, CStr},
ffi::c_char,
ptr::addr_of,
};
@ -94,15 +93,16 @@ fn panic_wrapper(panic_info: &core::panic::PanicInfo) -> ! {
uprint!("kernel panic: ");
}
if let Some(s) = panic_info.message() {
uprintln!("{}", s);
} else if let Some(s) = panic_info.payload().downcast_ref::<&str>() {
uprintln!("{}", s);
} else if let Some(s) = panic_info.payload().downcast_ref::<&CStr>() {
uprintln!("{:?}", s);
} else {
uprintln!("could not recover error message");
}
uprintln!("{}", panic_info.message().as_str().unwrap_or("could not recover error message"));
// if let Some(s) = panic_info.message() {
// uprintln!("{}", s);
// } else if let Some(s) = panic_info.payload().downcast_ref::<&str>() {
// uprintln!("{}", s);
// } else if let Some(s) = panic_info.payload().downcast_ref::<&CStr>() {
// uprintln!("{:?}", s);
// } else {
// uprintln!("could not recover error message");
// }
uprintln!("███████╗██╗ ██╗ ██████╗██╗ ██╗██╗██╗");
uprintln!("██╔════╝██║ ██║██╔════╝██║ ██╔╝██║██║");